FULLADDER:
A fulladder is a combinational circuit that forms the arithmetic
sum of three input bits. A fulladder consists of three inputs and two outputs.
Two of the input variables fulladder, denoted by x and y, represent the two
significant bits to be added. The third
input, z, represents the carry from the previous lower significant position. Two outputs of fulladder are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two output of fulladder are designated by the symbols S (for sum) and C (for carry). The binary variable S gives the value of the least significant bits of the sum. The binary variable C gives the output carry. The truth table of the fulladder is shown below. The eight rows under the input variables designate all possible combinations that the binary variables may have. The values of the output variables are determined from the arithmetic sum of the input bits. When all input bits of fulladder are 0, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output of the fulladder has a carry of 1 if two or three inputs are equal to 1. The K maps for fulladder are used to find algebraic expressions for the two output variables. The 1's in the squares for the maps of S and C are determined directly from the minterms in the truth table. The squares with 1's for the S output do not combine in groups of adjacent squares. But since the output is 1 when an odd number of inputs are 1, S is an odd function and represents the exclusiveOR relation of the variables. The squares with 1's for the C output may be combined in a variety of ways. One possible expression for C is xy + (x'y +xy')z. And including the expression for output S, we obtain the two Boolean expressions for the fulladder:S = x'y'z +x'yz' +xy'z' +xyz
the logic diagram of the fulladder is given below. Note that the full adder circuit consists of two halfadders and an OR gate.input, z, represents the carry from the previous lower significant position. Two outputs of fulladder are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary 2 or 3 needs two digits. The two output of fulladder are designated by the symbols S (for sum) and C (for carry). The binary variable S gives the value of the least significant bits of the sum. The binary variable C gives the output carry. The truth table of the fulladder is shown below. The eight rows under the input variables designate all possible combinations that the binary variables may have. The values of the output variables are determined from the arithmetic sum of the input bits. When all input bits of fulladder are 0, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output of the fulladder has a carry of 1 if two or three inputs are equal to 1. The K maps for fulladder are used to find algebraic expressions for the two output variables. The 1's in the squares for the maps of S and C are determined directly from the minterms in the truth table. The squares with 1's for the S output do not combine in groups of adjacent squares. But since the output is 1 when an odd number of inputs are 1, S is an odd function and represents the exclusiveOR relation of the variables. The squares with 1's for the C output may be combined in a variety of ways. One possible expression for C is xy + (x'y +xy')z. And including the expression for output S, we obtain the two Boolean expressions for the fulladder:S = x'y'z +x'yz' +xy'z' +xyz
LOGIC DIAGRAM AND TRUTH TABLE OF FULL ADDER
The logic diagram, block diagram and truth table is shown
below. The logic diagram is implemented by two XOR gates, two AND gates and OR
gate. The given XOR gates are used to obtain the sum output of the fulladder
and other logic gates are used to get the carry output of the fulladder. The Kmap
for obtaining sum output and carry output is also given below.
INPUT

OUTPUT


X

Y

Z

C

S

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

IMPLEMENTATION OF FULLADDER USING 3TO8 LINE DECODER:
Here, It is a truth
table for a fulladder which add 3 bit A, B, and C_{in} simultaneously ,
where A and B are addend and augend bits respectively, C_{in} is carry
in from the previous bits (if any). Here, S, C_{out }are the outputs
where S is the sum of the fulladder and c_{out} is the carry out of
the fulladder. Now we can write,
S = F (A, B, C_{in}) = ∑_{m }(1,
2, 4, 7) and C_{out }= F (A, B, C_{in}) =
∑_{m }(3, 5, 6, 7)
Now, the given requirement of designing a fulladder using decoder can be implemented by a 3to8 line decoder. Since, a decoder is a minterm generator, we can use those minterms of decoder which present the Boolean function of sum (S) and carry (C_{out}).
Now, the given requirement of designing a fulladder using decoder can be implemented by a 3to8 line decoder. Since, a decoder is a minterm generator, we can use those minterms of decoder which present the Boolean function of sum (S) and carry (C_{out}).
The figure shows the logic circuit diagram of fulladder using decoder and two OR gates. Here A, B, and C_{in }are inputs to decoder. EN is enable input which follows active high logic. Y_{0} to Y_{7 }are the eight minterms which are from m_{0 }to m_{8}. No, fulladder gives the sum output 1 only when m_{1 }or m_{2 }or m_{4 }or m_{7 }_{ }is 1. So, we can write S = m_{1}+m_{2}+m_{4}+m_{7}. Similarly fulladder gives the C_{out} output 1 only when m_{3} or m_{5} or m_{6} or m_{7} is 1. So, we can write C_{out} = m_{3}+m_{5}+m_{6}+m_{7}
IMPLEMENTATION OF FULL ADDER USING HALF ADDERS AND LOGIC GATES
A Full Adder can be made using Half Adders and logic gates like ANDgates, OR gate. To implement this circuit two Half Adders, one OR gate, and two AND gates are used. These two Half Adders are named by HA1 and HA2. First Half Adder HA1 has two inputs X and Y respectively, S (for sum) and C (for carry) are the two outputs of the HA1, where S = X'Y+XY' and C = XY, where S and C are the sum output and carry output of HA1. The output S of first HA1 is the first input of HA2, Z is the second input to the HA2, S’ is the sum output of the second HA2 that is equal to XY'Z'+X'YZ'+X'Y'Z+XYZ and it is the sum output of a Full Adder. To get carry output of the Full Adder logic gates are used. The carry output of a Full Adder is XY + XZ + YZ, where X, Y, and Z are the inputs. To get this output two AND gates and one OR gate is used, the first AND gate has the inputs X and Z and generates the output XZ, similarly the second AND gate has two inputs Y and Z and produces the output YZ. These two outputs XZ and YZ as well as the output XY of the HA1 is used as three inputs for the OR gate. This OR gate generates the output XY+YZ+XZ that is equivalent to the carry output of a Full Adder. The logic diagram of the Full Adder using Half Adder and logic gates is given below.IMPLEMENTATION OF FULLADDER USING MUX OR MULTIPLEXER
From the above truth table of FullAdder and information supplied we know
that the sum output and carry output of a FullAdder is as written:
S = F (A, B, C_{in}) = ∑(1, 2, 4,
7) and C_{out }= F (A, B, C_{in})
= ∑(3, 5, 6, 7).
Where A, B, C_{in }are the inputs to the FullAdder. S and C_{out
}are the sum output and carry output respectively. Now, the given requirement of designing a FullAdder using MUX
(Multiplexer) can be implemented by 2X1 MUX or 4X1 MUX or 8X1 MUX.
IMPLEMENT OF FULLADDER USING 8X1 MUX OR MULTIPLEXER
At first we are going to implement this FullAdder by 8X1 Multiplexer. To implement
this circuit we need two 8X1 Multiplexers the first one gives the output for
sum output of FullAdder and second gives output for carry output of
FullAdder. The general output equation of a 8X1 MUX or Multiplexer is as follows:
Y = I_{0}S’_{2}S’_{1}S’_{0}
+ I_{1}S’_{2}S’_{1}S_{0} + I_{2}S’_{2}S_{1}S’_{0}
+ I_{3}S’_{2}S_{1}S_{0} + I_{4}S_{2}S’_{1}S’_{0}
+ I_{5}S_{2}S’_{1}S_{0} + I_{6}S_{2}S_{1}S’_{0}
+ I_{7}S_{2}S_{1}S_{0} …..(1)
Where Y is the output of 8X1 MUX or Multiplexer S_{2}, S_{1} and S_{0}
are the selection inputs to the MUX and I_{0}, I_{1}, I_{2},
I_{3}, I_{4}, I_{5}, I_{6} and I_{7}
are the inputs to the multiplexer.
Now, the output equation of the sum output of FullAdder is as follows:
S=F(A,B,C_{in})=∑(1,2,4,7) = m_{1} + m_{2}
+ m_{4} +m_{7}
_{ }= A’B’C_{in} + A’BC’_{in} + AB’C’_{in}
+ ABC_{in}
= 0.A’B’C’_{in}
+ 1.A’B’C_{in} + 1.A’BC’_{in} + 0.A’BC_{in} + 1.AB’C’_{in}
+ 0.AB’C_{in} 0.ABC’_{in} + 1.ABC_{in} ………………………………. (2)
Now, comparing equations (1) & (2) we get
I_{0} = 0, I_{1} = 1, I_{2} = 1, I_{3} =
0, I_{4} = 1, I_{5} = 0, I_{6} = 0 and I_{7} =
1. And S_{2} = A, S_{1} = B and S_{0} = C_{in}.
These values are for first multiplexer for sum output of FullAdder. Now, we will find all values for second MUX for carry output of FullAdder. The general output equation of carry output is as follows:
These values are for first multiplexer for sum output of FullAdder. Now, we will find all values for second MUX for carry output of FullAdder. The general output equation of carry output is as follows:
C_{out }= F (A, B, C_{in}) = ∑(3, 5, 6, 7)
= m_{3} + m_{5}
+ m_{6} + m_{7}
= A’BC_{in}
+ AB’C_{in} + ABC’_{in} + ABC_{in}
= 0.A’B’C’_{in} + 0.A’B’C_{in} + 0.A’BC’_{in}
+ 1.A’BC_{in} + 0.AB’C’_{in} + 1.AB’C_{in} 1.ABC’_{in}
+ 1.ABC_{in }…………………………… (3)_{ }
Comparing the equations (1) & (3) we have
I_{0} = 0, I_{1} = 0, I_{2} = 0, I_{3} =
1, I_{4} = 0, I_{5} = 1, I_{6} = 1 and I_{7} =
1. And S_{2} = A, S_{1} = B and S_{0} = C_{in}.
These values are for second multiplexer for carry output of FullAdder.
Now, we have all the values of the two multiplexers therefore the circuit
of the FullAdder can be implemented. The block diagram of FullAdder is shown here.
IMPLEMENTATION OF FULLADDER USING 4X1 MUX OR MULTIPLEXER
SEE MORE
IMPLEMENTATION OF FULLADDER USING 4X1 MUX OR MULTIPLEXER
We already know the sum output and carry output of a FullAdder. Now, we
have to write the general output equation of a 4X1 MUX or Multiplexer and it is as follows:
Y = I_{0}S’_{1}S’_{0} + I_{1}S’_{1}S_{0} + I_{2}S_{1}S’_{0} + I_{3}S_{1}S_{0} …………………………………. (1)
Where Y is the output of the MUX or Multiplexer S_{1 }and S_{2} are the
selection inputs. From I_{0} to I_{3 }are the inputs to the
MUX or Multiplexer.
Now, the output equation of the sum of FullAdder is as follows:
S = F(A,B,C_{in})
= ∑(1,2,4,7)
= m_{1} + m_{2} + m_{4} +m_{7}
= ∑(1,2,4,7)
= m_{1} + m_{2} + m_{4} +m_{7}
= A’B’C_{in}
+ A’BC’_{in} + AB’C’_{in} + ABC_{in}
= A.(B’C’_{in}) + A’.(B’C_{in}) + A’.(BC’_{in}) + A.(B’C’_{in})……………………(2)
= A.(B’C’_{in}) + A’.(B’C_{in}) + A’.(BC’_{in}) + A.(B’C’_{in})……………………(2)
Comparing equations (1) & (2) we have
Now, the output equation of carry output of FullAdder is as follows:
C_{out }= F (A, B, C_{in}) = ∑(3, 5, 6, 7)
= m_{3} + m_{5} + m_{6}
+ m_{7}
=
A’BC_{in} + AB’C_{in} + ABC’_{in} + ABC_{in}
= (A’
+ A) BC_{in} + AB’C_{in} + ABC’_{in} + 0.AB’C’_{in }[since A + A’ = 1]
_{ }= 0.(B’C’_{in}) + A.(B’C_{in})
+ A.(BC’_{in}) + 1.(BC_{in})
………………………(3)
Comparing equation (1) and (2) we have
I_{0} = 0, I_{1} = A, I_{2} = A, I_{3} = 1 and S_{1} = B, S_{0} = C_{in}.
I_{0} = 0, I_{1} = A, I_{2} = A, I_{3} = 1 and S_{1} = B, S_{0} = C_{in}.
The logic diagram of FullAdder using 4X1 MUX or Multiplexer is shown here.
From the above picture, it can be shown that a FullAdder can be
implemented by two 4X1 MUX or Multiplexers. One MUX or Multiplexer is used to find the sum of the FA (FullAdder)
and other is used to get the carry output of FA. Each 4X1 MUX has two selection
input lines which are used to select one of the inputs from I_{0} to I_{3}.
Here, two selection inputs of each 4X1 MUX or Multiplexers are replaced by the two inputs of
FullAdder B and C_{in} and the values of I_{0 }to I_{3}
of each 4X1 MUX has given.
IMPLEMENTATION OF FULLADDER USING 2X1 MUX OR MULTIPLEXER
Here, it is implemented by 2X1 MUX. The general output equation of 2X1
MUX is written as:
Y = I_{0}S’_{0}
+ I_{1}S_{0 } ……………………………………. (1)
Where Y is the output to MUX, S_{0} is the selection input to the
MUX and I_{0} and I_{1} are the inputs to MUX.
Now, output equation of sum output FullAdder is as follows:
S = F(A,B,C_{in}) = ∑(1,2,4,7) = m_{1} + m_{2} + m_{4} +m_{7}
_{ }= A’B’C_{in}
+ A’BC’_{in} + AB’C’_{in} + ABC_{in}
= (A’B + AB’).C’_{in} + (A’B’ + AB).C_{in} …………………………………. (2)
Comparing equations (1) & (2) we get
I_{0} = A’B + AB’, I_{1} = A’B’ + AB and S_{0} =
C_{in}.
Now, output equation of carry out of FullAdder is as follows:
C_{out }= F (A, B, C_{in})
= ∑(3, 5, 6, 7)
= m_{3} + m_{5} + m_{6} + m_{7}
= A’BC_{in} + AB’C_{in} + ABC’_{in} + ABC_{in}
= (AB)C_{in} + (A’B + AB’ + AB)C_{in}
_{ }= (AB)C_{in}
+ (A + B)C_{in} …………………......(3)
Comparing equation (1) & (3) we have
I_{0} = AB, I_{1} = A + B and S_{0} = C_{in}.
IMPLEMENTATION OF FULLADDER USING NAND GATE
The circuit diagram of a Fulladder can be implemented by using only NAND gates because we know that NAND gates are called universal logic gates. A universal gates means a gate which is alone sufficient to implement any circuit. Hence, the circuit of the Fulladder using NAND gates is shown below. We know that the sum output of Fulladder and the carry output is as follows:
S = F(A,B,C_{in}) = ∑(1,2,4,7) = m_{1} + m_{2} + m_{4} +m_{7}
_{ }= A’B’C_{in} + A’BC’_{in} + AB’C’_{in} + ABC_{in}
and, C_{out }= F (A, B, C_{in}) = ∑(3, 5, 6, 7)
= m_{3} + m_{5} + m_{6} + m_{7}
= A’BC_{in} + AB’C_{in} + ABC’_{in} + ABC_{in}
= AB + AC_{in} + BC_{in} (After solving the equation)
To implement the circuit by NAND gates first we have to take the double complement of the sum output and carry output. After complementing two times the sum output and carry output, the terms of the obtained output equations are the output of each NAND gates and all these output are directed as input to a NAND gate which gives the final outputs.
_{ }{(S)'}' = {( A’B’C_{in} + A’BC’_{in} +
AB’C’_{in} + ABC_{in })'}'_{ }
_{ }S = { (A’B’C_{in})’. (A’BC’_{in})’.
(AB’C’_{in})’. (ABC_{in})’}’
and,
{(C_{out})’}’= {(AB + AC_{in} + BC_{in})’}’
C_{out} = {(AB)’. (AC_{in})’.(BC_{in})’}’_{ }
The circuit diagram
of the fulladder using NAND gates are shown below.
IMPLEMENTATION OF FULLADDER USING NOR GATES
Designing the
circuit diagram of a FullAdder using NOR Gates can be done by as we done above
with NAND Gates. There a few steps we need to take to construct the circuit and
these steps are listed below.
 Change the sum output and Carry output equations into Canonical form.
 Change the sum output and carry output equations into sum of product forms.
 Take double complement of sum output equation and carry output equation.
Since the Sum
output of the FullAdder is in canonical form and also in product of sum form
so we have to execute the second step. Here we will use KMap to convert the
output equations into SOP form.
X(A, B, C) = A’B’C+A’BC’+AB’C’+ABC
X(A, B, C) = ∑_{m }(1, 2, 4,
7)
Here KMap for
Sum output is shown. To find the SOP form we have to cover the all zeros as the
combinations of them should be minimum. One thing we need to know that the
covering is done either horizontally or vertically with adjacent same value.
Since in the above map there are no adjacent zeros either vertically or
horizontally. By covering zeros we find the complement of the sum output. Thus
we get
X’ = A’B’C’+A’BC+AB’C+ABC’
Now take
Complement of S’, we obtain the simplified function in product of sum form:
(X’)’ =
(A+B+C)(A+B’+C’)(A’+B+C’)(A’+B’+C)
X = (A+B+C)(A+B’+C’)(A’+B+C’)(A’+B’+C)
Similarly we
can change the carry output equation into product of sum form.
The carry
output equation is Y = AB+BC+AC. Since the equation is not in canonical form so
at first we will change it in canonical form.
Y = AB+BC+AC
Y = AB.1+BC.1+AC.1
Y = AB(C+C’)+BC(A+A’)+AC(B+B’)
Y = ABC+ABC’+ABC+A’BC+ABC+AB’C
Y = ABC+ABC+ABC+A’BC+AB’C+ABC’
Y = ABC+ A’BC+AB’C+ABC’
Now the carry
output equation has been changed into canonical form. Thus perform the second
step.
Y(A, B, C) = ABC+ A’BC+AB’C+ABC’
Y(A, B, C) = ∑_{m }(3, 5, 6,
7)
KMap for
carry output is shown above. From the above KMap we can write:
Y’ = A’B’+B’C’+A’C’
Taking complement
of X’ we obtain the product of sum form of carry output:
(Y’)’
= (A+B)(B+C)(A+C)
Y = (A+B)(B+C)(A+C)
Now we will
take last step,
X = (A+B+C)(A+B’+C’)(A’+B+C’)(A’+B’+C)
(X’)’ = [{(A+B+C)(A+B’+C’)(A’+B+C’)(A’+B’+C)}’]’
X = [(A+B+C)’+(A+B’+C’)’+(A’+B+C’)’+(A’+B’+C)’]’
Similarly
Y = (A+B)(B+C)(A+C)
(Y’)’ = [{(A+B)(B+C)(A+C)}’]’
Y = [(A+B)’+(B+C)’+(A+C)’]’
Using X = [(A+B+C)’+(A+B’+C’)’+(A’+B+C’)’+(A’+B’+C)’]’
and Y = [(A+B)’+(B+C)’+(A+C)’]’ we will design the circuit. The circuit of FullAdder
using NOR Gates is shown below.
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