Home » Flip-Flop

Category Archives: Flip-Flop

T FLIP FLOP

T FLIP FLOP BLOCK DIAGRAMAnother type of flip flop is the T (toggle) flip flop. It is also called toggle flip flop. This flip flop is obtained from a JK flip flop when inputs J and K are connected to provide a single input designated by T. The T flip flop therefore has only two conditions. When T = 0 (J = K = 0) a clock transition does not change the state of the flip flop. When   T =1 (J = K = 1) a clock transition complements the state of the flip flop. The excitation table of flip flop is output oriented while the characteristic table of the flip flop is  input oriented. The excitation table and characteristic table of T flip flop are shown here. These conditions can be expressed by a characteristic equation. Q (t+1) = Q'(t) T + Q (t) T’

TRUTH TABLE EXCITATION TABLE AND CHARACTERISTIC TABLE OF T FLIP FLOP

CONVERSION OF T FLIP FLOP INTO OTHER FLIP FLOPS:

A T flip flop can be converted into other flip flops by inserting some logic gate in the logic diagram of T flip flop. A D flip flop can be obtainedJK FLIP FLOP USING T FLIP FLOP by adding a XOR gate before the T input line. This gate has two inputs line which of them one is D input (means the input for D flip flop) and the second input comes from the output Q of flip flop T. Similarly a T flip flop can be converted into a JK flip flop. To get the output of a JK flip flop from a T flip flop, we have to add a small circuit before T input of the flip flop. Two AND gates and one OR gate are combined in such a way that they give input to the T flip flop either 0 or 1. From the figure given below we can see, each AND gate has two inpuD FLIP FLOP USING T FLIP FLOPts. The first AND gate has input J and another input from the complemented value of Q of the T flip flop. Similarly the second AND gate has input K and another input line from output Q of the T flip flop. The outputs of these two logic gates are the inputs for OR gate and the output of OR gate generates the input either 0 or 1 for the T flip flop and these inputs works as inputs for JK flip flop and generate the required output of JK flip flop.

CIRCUIT DIAGRAM OF T FLIP FLOP USING NAND GATE:

CIRCUIT DIAGRAM OF T FLIP FLOP USING NAND GATEThe circuit diagram of the T flip flop can be made using NAND gates. We use four NAND gates to implement this whole circuit of T flip flop. The first two NAND gates have three inputs, the first input is T input which is common to both NAND gates, the second input is common CLK (clock) input which makes the whole circuit active and inactive and the third  inputs are form the outputs Q and Q’ (complement of Q) of T flip flop. The last two each NAND gates have two inputs one from the outputs of first two NAND gates and one from the each outputs Q and Q’ of T flip flop.

USE OF T FLIP FLOP:

It can be used as a counter. There are different types of counter like synchronous counter, a synchronous counter and ripple counter. A 3 bit ripple up and down counter is shown below. To implement this counter we need three T flip flops. The T input is equal to 1. There are two more input which is preset input and clear input abbreviated as PRE and CLR. Here (PRE)’ and (CLR)’ denote the complement of preset input and of clear input. Q2Q1Q0gives the output for up counter while Q’2Q’1Q’0gives the output of down counter and where Q2 and Q’2 are most significant bits and Q0 and Q’0 are least significant bits. CLK is the clock input to the flip flop. As we can see that Q’ output of each flip flop is directed as input to its next flip flop as clock input to make the flip flops active. The PRE and CLR inputs are 1 and 0 here.
3 BIT RIPPLE COUNTER USING T FLIP FLOP

JK FLIP FLOP

A JK flip flop is a refinement of the SR flip flop in that the indeterminate condition of the SR type is defined in the JK type.Inputs J and K behave like input S and R to set and clear thBLOCK DIAGRAM OF JK FLIP FLOPe flip flop, respectively. When inputs J and K both are equal to 1,a clock transition switches the output of the flip flop to their complement state. The graphical symbol and characteristic table of the JK flip flop are shown here.The input J input is equivalent to the S (set) input of the SR flip flop, and the K input is equivalent to the R(clear) input. Instead of the indeterminate condition, the JK flip flop has a complement condition Q(t+1) = Q(t) when both J and K are equal to 1.

CONVERSION OF JK FLIP FLOP INTO OTHER FLIP FLOPS:

BLOCK DIAGRAM OF T FLIP FLOP USING JK FLIP FLOPBLOCK DIAGRAM OF D FLIP FLOP USING JK FLIP FLOP
A JK flip flop can be converted into a D flip flop by joining the two inputs of the JK flip flop into a single input inserting a NOT gate between them and this single input is named as D input of the Flip flop. This single input works as input for D flip flop. As we can see we have included a NOT gate at K input so that when we give a input to the flip flop it can generate two values one is its normal value and one is its complemented value, suppose we assign 0 to the D input of flip flop the input J receives input 0 and input K gets input 1 and the output generated here is 0. For input 1 it gives 1. Similarly A T flip Flop can also be implemented by joining two inputs J and K into a single input named T. Here, we do not insert any NOT gate between the inputs J and K. When we take input 0 it gives output Q(t) because both the inputs J and K have input 0 and for these values of J and K the JK flip flop has output Q(t) where Q(t) is its previously stored vale. And for 1 it gives output Q'(t) these results are obtained from characteristic table of JK flip flop.

CIRCUIT DIAGRAM OF JK FLIP FLOP USING NAND GATES:

BLOCK DIAGRAM OF JK FLIP FLOP USING NAND GATESThe circuit diagram of JK flip flop can be implemented either by NAND gates or NOR gates but we will implement this circuit here with NAND gates. We require four NAND gates to implement this whole circuit diagram. The two each NAND gates have three inputs. They have a common clock input to the circuit active and inactive. From the picture shown below we can state that NAND gate 1 has input J, common CLK (clock input) input and an input from Q'(complement of Q), similarly NAND gate 3 has input K, common input CLK and an input from output Q. The last two NAND gates have two inputs each. The NAND gate 2 has two inputs one is the output from NAND gate 1 and one from output Q’, in the same way NAND gate 4 has inputs from NAND gate 3 and from output Q of the flip flop. This is the required circuit diagram of the JK flip flop using NAND gates.

DRAWBACK OF JK FLIP FLOP:

In spite of the added advantage over SR flip flop of indeterminate condition, JK flip flop suffers from a serious limitation which is called race condition. If the JK flip flop is at the positive pulse of the clock input as long as the J and K inputs are equal to 1 the output of the JK flip flop goes on toggling and makes unwanted oscillation at output Q and Q’ (read as Q complement). As a matter of consequence Q may be indeterminable at J = K = 1, this condition is called race condition. This problem can be solved using master slave JK flip flop.

D FLIP FLOP

The D (data) flip flop is a slight modification of the SR flip flop. An SR BLOCK DIAGRAM OF D FLIP FLOPflip flop is converted to a D flip flop by inserting an INVERT GATE (NOT gate) between S and R and assigning the symbol D to the signal input. The D input is sampled during the occurrence of a clock transition from 0 to 1. If D = 1, The output of the flip flop goes to the 1 state, but if D = 0 the output of the flip flop goes to the 0 state.  The graphic symbol and characteristic table of the D flip flop are shown below. From the characteristic table which is shown below,  we note that the next state Q(t+1) is determined from the D input. The relationship can be expressed by a characteristic equation Q(t+1) = D. This means that the Q output of the flip flop receives its value from the D input every time that the clock signal goes through a transition from 0 to 1. Note that no input condition exist that will leave the state of the D flip flop unchanged.Although the D flip flop has a advantage of having only one input (excluding C), it has the disadvantage that its characteristic table does not have a no change condition Q(t+1) = Q(t). The no change condition can be accomplished either by disabling the clock signal or by feeding the output back into the input, so that clock pulse keep the state of the flip flop unchanged.

IMPLEMENTATION OF JK FLIP FLOP FROM D FLIP FLOP:

JK FLIP-FLOP USING D FLIP FLOP

A JK flip flop can be implemented from a D flip flop. A D flip flop has a single input line but in the a JK flip flop there are two input lines so we have to add some logic gates in such a way that there can be generated  two input J and K. From the figure shown below we can see that there is a small circuit of LOGIC GATES before the single input of D flip flop. These gates are used to generate two inputs J and K. Each AND gate has two input lines one has input J and a input from output Q'(complement of Q) of the D flip flop and the second AND GATE has a input K as well as input from output Q of the D flip flop. The outputs of the two AND gates are directed to an OR GATE and whose output is the input for the D flip flop. The required diagram is given below.

CIRCUIT DIAGRAM OF D FLIP FLOP USING NAND GATE:

CIRCUIT DIAGRAM OF D FLIP FLOP USING NAND GATE

The circuit diagram of D flip flop by using NAND GATES is shown below. There are four NAND gates in this circuit diagram and each NAND gate has two inputs. The first two NAND gates have a common CLK input (CLOCK INPUT) and a common D input. The last two NAND gates have inputs. They have inputs from the output of previous NAND gates and form the outputs Q and Q’ (READ AS Q COMPLEMENT)  of the flip flop.

SR FLIP FLOP

Block Diagram of SR Flip FlopExcitation Table of SR Flip FLopThe graphic symbol of the SR flip flop is shown below. An SR flip flop has three inputs, S, R,and C, where S is  for set, R is for reset of flip flops and C is the clock input which enables and disables the flip flop. It has an output Q and sometimes the flip flop has a complemented output, that is indicated with a small circle at the other output terminal. There is an arrowhead-shaped symbol in front of the letter C to designate a dynamic input. The dynamic indicator symbol denotes the fact that the flip flop responds  to a positive transition (from 0 to 1) of the input clock signal. The operation of a SR flip flop is as follows. If there is no signal at the clock input C, the output of the circuit cannot change irrespective of the values at inputs S and R. Only when the clock signal changes from 0 to 1 the output can be affected according to the values in inputs S and R. If S = 1 and R = 0 when C changes from 0 to 1, output Q is set to 1. If S = 0 and R = 1 when C changes from 0 to 1, output Q is cleared to 0. If both S and R are 0 during the clock transition, the output does not change. When both are equal to 1, the output is unpredictable and may go to 0 or 1, depending on internal timing delay that occur within the circuit. The characteristic table of the SR flip flop shown below summarises the operation of the SR flip flop in the tabular from. The S and R columns give the binary values of the two inputs. Q(t) is the binary state of the Q output at a given time (referred t a as present state). Q(t+1) is the binary state of the Q output after the occurrence of a clock transition (referred to as next state). If S=R=0, a clock transition produces no change of state that means Q(t+1) is equal to Q(t). If S=0 and R=1, the flip flop goes to the 0(clear) state. If S=1 and R=0, the flip flop goes to 1(set) state. The SR flip flop should not be pulsed when S=R=1 since it produces an indeterminate next state. This indeterminate condition makes the SR flip flop difficult to manage and therefore it is seldom used in practise. The excitation table and characteristic table of SR flip flop is shown above, where characteristic table is input oriented and excitation table is output oriented.

IMPLEMENTATION OF OTHER FLIP FLOPS FROM SR FLIP FLOP:

Implementation of JK flip flop from SR flip flop is given below. An SR flip flop can be converted into a JK flip flop by inserting two AND gates to circuit. We aBlock Diagram of D Flip Flop Using SR Flip Flopdd these two AND gates at S and R input lines to obtain the the input of  J and K. The AND gate that is joined at S input has two inputs J and an input line from Q’ of the flip flop. Similarly the AND gate at R input also has two inputs K and an input from the output Q of the flip flop. This is how a SR flip flop is converted into a JK flip flop and its block diagram is shown below. Formation of D flip flop form an SR flip flop is shown below. To implement this circuit the input lines S and R are connected by a common input D which has a NOT gate at R input.

Block Diagram of JK flip Flop Using SR Flip FlopBlock Diagram of T flip Flop Using SR Flip Flop

CIRCUIT DIAGRAM OF SR FLIP FLOP USING NAND GATES:

The circuit diagram of SR flip flop is illustrated below. NAND gates are usedBlock Diagram of SR Flip Flop Using NAND Gates here to implement this circuit. Four NAND gates are used to implement this circuit. They have a common clock input which makes the whole circuit active and inactive. Form the first two NAND gates we can see one NAND gate has a input S and a input line from clock input and the second NAND gate has a input R and a input line from clock input. From last two NAND gates we can say that each also have two inputs. One has a input from its previous NAND gate and from output Q’ and second has a input Q and from its previous NAND gate. So this is the way to implement this circuit. The circuit shown below.

DRAWBACK OF SR FLIP FLOP:

In active high logic of clock pulse S and R inputs of SR flip flop are equal to 1 and in active low logic of they equal to 0. For these two condition of the two inputs of SR flip flops, the SR flip flop does not follows the complementary output of flip flop, since there are two outputs Q and Q’ and they should be complement of each other but it is not followed when S = R = 1 (active high) and S = R = 0 (active low) for this reason SR flip flop is disregarded.

FLIP FLOP AND ITS TYPES

The digital circuits considered thus far have been combinational, where the outputs at any given time are entirely dependent on the inputs that are present at that time. Although every digital system is likely to have a combinational circuit, most systems encountered in practice also include storage elements, which require that the system be described in terms of sequential circuits. The most common type of sequential circuit is the synchronous type . Synchronous sequential circuits employ signals that affects the storage elements only at discrete instants of time. Synchronization is achieved by a timing device called a clock pulse generator that produces a periodic train of clock pulse. The clock pulse are distributed throughout the system in such a way that storage elements are affected only with the arrival of the synchronization pulse.Clocked synchronous sequential circuits are the type most frequently encountered in practice. They seldom manifest instability problems and their timing is easily broken down into independent discrete steps, each of which may be  considered separately.The storage elements employed in clocked sequential circuits are called flip flops. A flip fop is a binary cell capable of storing one bit of information. It has bit stored in it. A flip flop maintains a binary state until directed by a clock pulse of inputs they possess and in the manner which the inputs affect the binary state.The most common types of flip flops are presented below.

CLOCK PULSE DIAGRAM OF FLIP FLOP

TYPES OF FLIP FLOP

Various types of flip flops can be found. The most common types of flip flops are listed below.

  1. SR Flip Flop
  2. D Flip Flop
  3. JK Flip Flop
  4. T Flip Flop
  5. Edge Triggered Flip Flop