### TRUTH TABLE AND BLOCK DIAGRAM OF TWO INPUT XNOR GATE

### TRUTH TABLE AND BLOCK DIAGRAM OF THREE INPUT XNOR GATE

### IMPLEMENTATION OF TWO INPUT XNOR GATE USING BASIC GATES

### IMPLEMENTATION OF THREE INPUT XNOR GATE USING BASIC GATES

The output of a three input XNOR gate is ABC’+AB’C+A’BC+A’B’C’. Where A, B and C are inputs to XNOR gate to implement a three input XNOR gate using basic gates (AND gate, OR gate and NOT gate) it requires four three input AND gates three NOT gates and one four input OR gate. NOT gates are used to find inverted inputs of inputs A, B and C. The first AND gate has inputs A, B and C’ and produces output ABC’ now the Second AND gate has input A, B’ and C and produces output AB’C similarly third and fourth AND gates has inputs A, B and C’ and A’, B’ and C’ respectively and produce outputs ABC’ and A’B’C’. Now these four outputs of AND gates are inputs to the OR gate and this four input OR gate generates output ABC’+AB’C+A’BC+A’B’C’.

### IMPLEMENTATION OF XNOR GATE USING UNIVERSAL NAND GATES

Now we can implement the circuit of two inputs XNOR gate using NAND gates. To implement two input XNOR gate it will take three two input NAND gates and two single input NAND gates. Single input NAND gates are used to find compliments of inputs A and B. Thus single input NAND gates produces output A’ and B’ that are used as inputs to second NAND gate and it produces output (A’B’)’. The first NAND gate has inputs A and B and produces output (AB)’. The outputs (AB)’ and (A’B’)’ are fed as inputs to the third NAND gate and it process the final output [(AB)’ (A’B’)’]’ which is equivalent to AB + A’B’.

Now implementation of XNOR gate using NAND gates can be started. It needs four three input NAND gates, one four input NAND gates and three single input NAND gates. Three single input NAND gates are used as NOT gates to find A’, B’ and C’. The first three input NAND gate has inputs A, B and C’ and produces output ABC’. The second three input NAND gate has inputs A, B’ and C and produces output AB’C. Third and fourth three input NAND gates have inputs A’, B and C and A’, B’ and C’ respectively and produce output A’BC and A’B’C’. These four outputs ABC’, AB’C, A’BC and A’B’C’ are used as input for four input NAND gate. The four input NAND gate finally produces output [(ABC’)’(AB’C)’(A’BC)’(A’B’C’)’]’ which is equal to ABC’+AB’C+A’BC+A’B’C’.

### IMPLEMENTATION OF XNOR GATE USING UNIVERSAL NOR GATES

Now the implementation of two input XNOR gate can be started using NOR gates. To implement this circuit it needs three two input NOR gates and two single input NOR gate to find A’ and B’ of inputs A and B. First NOR gate having input A’ and B will produce output (A’ + B)’ and the Second NOR gate having inputs A and B’ will produce output (A + B’)’. These two outputs are fed as input to third NOR gate and this NOR gate produces output [(A’ + B)’ + (A + B’)’]’. The output of three input XNOR gate is Y = ABC’+AB’C+A’BC+A’B’C’ and it is not in POS form. Therefore it needs to be changed into POS form.