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# XNOR GATE (EXCLUSIVE-NOR GATE)

XNOR gate is the complement of the exclusive-OR gate. It is obtained by adding a NOT gate next to a XOR gate. The NOT gate is indicated by a small circle in the block diagram given here.

### TRUTH TABLE AND BLOCK DIAGRAM OF TWO INPUT XNOR GATE

Form the block diagram shown here, it can be said that a XNOR gate can be obtained by putting a circle which represent a NOT gate after a XOR gate. From the block diagram it can be seen that it has two inputs A and B, and an output Y which is equivalent to the complemented output of a two input XOR gate. So, the output of XNOR gate is Y is equal to (A’B + AB’)’.

Y = (A’B + AB’)’
By De Morgan’s theorem the output can be written as
= (A’B)’. (AB’)’
= (A + B’)(A’ + B)
= AA’ + B’A’ + AB + BB’
Since AA’ and BB’ are equal to zero by Postulates of Boolean algebra
= AB + A’B’
Now after solving the output Y is equal to AB + A’B’. A two input XNOR gate gives the output 1 when both inputs are equal to 1 or when both inputs are equal to 0. The block diagram and truth table of the two input XNOR gate is shown here.

### TRUTH TABLE AND BLOCK DIAGRAM OF THREE INPUT XNOR GATE

Y = (A’B’C+A’BC’+AB’C’+ABC)’Logic diagram or block diagram of a three input XNOR gate is shown here. A, B, and C are the three inputs and Y is the output of XNOR gate. The output of a three input XNOR gate is equal to (A’B’C+A’BC’+AB’C’+ABC)’.
Applying De Morgan’s theorem the output of three input XNOR gate be written as
= (A’B’C)’(A’BC’)(AB’C’)(ABC)’
Now applying De Morgan theorem again we get
= (A + B + C’)(A + B’ + C)(A’ + B + C)(A’ + B’ + C’)
After multiplying and solving we get
= ABC’+AB’C+A’BC+A’B’C’
Thus the output after solving is equal to ABC’+AB’C+A’BC+A’B’C’.
The output of a three input XNOR gate is 1 when all three inputs are equal to 0 or any two inputs are equal to 1 and the output is 0 when all three inputs are equal to 1 or any one of the three inputs is 1. The block diagram and truth table of three inputs XNOR gate is shown here.

### IMPLEMENTATION OF TWO INPUT XNOR GATE USING BASIC GATES

A two input XNOR gate or Exclusive-NOR gate can be implemented by using two AND gates, two NOT gates and one OR gate. The output of a two input XNOR gate is AB + A’B’ where A and B are inputs. NOT gates are used to get inverted inputs A and B. First AND gate is used to get output AB whose inputs are A and B. And Second AND gate is used to get output A’B’ whose input are A’ and B’. Now the two outputs AB and A’B’ are used as two inputs for the OR gate to find final output and it produces final output AB + A’B’. We can verify this circuit using a truth table.

### IMPLEMENTATION OF THREE INPUT XNOR GATE USING BASIC GATES

The output of a three input XNOR gate is ABC’+AB’C+A’BC+A’B’C’. Where A, B and C are inputs to XNOR gate to  implement a three input XNOR gate using basic gates (AND gate, OR gate and NOT gate) it requires four three input AND gates three NOT gates and one four input OR gate. NOT gates are used to find inverted inputs of inputs A, B and C. The first AND gate has inputs A, B and C’ and produces output ABC’ now the Second AND gate has input A, B’ and C and produces output AB’C similarly third and fourth AND gates has inputs A, B and C’ and A’, B’ and C’ respectively and produce outputs ABC’ and A’B’C’. Now these four outputs of AND gates are inputs to the OR gate and this four input OR gate generates output ABC’+AB’C+A’BC+A’B’C’.

### IMPLEMENTATION OF XNOR GATE USING UNIVERSAL NAND GATES

To implement a two input XNOR gate using only NAND gaTwo input and three input XNOR gates can be implemented using universal NAND gates. A NAND gate is called a universal gate because it is alone sufficient to implement any Boolean circuit.
tes we need to take double compliment of the output. Since the output of two input XNOR gate is Y = AB + A’B’. Now taking double compliment of output equation Y = AB + A’B’.
Y = AB + A’B’
(Y’)’ = [(AB + A’B’)’]’
Since (Y’)’ = Y therefore
Y = [(AB + A’B’)’]’
Applying De Morgan’s theorem
Y = [(AB)’ (A’B’)’]’
Since by De Morgan’s theorem (A + B)’ = A’B’

Now we can implement the circuit of two inputs XNOR gate using NAND gates. To implement two input XNOR gate it will take three two input NAND gates and two single input NAND gates. Single input NAND gates are used to find compliments of inputs A and B. Thus single input NAND gates produces output A’ and B’ that are used as inputs to second NAND gate and it produces output (A’B’)’. The first NAND gate has inputs A and B and produces output (AB)’. The outputs (AB)’ and (A’B’)’ are fed as inputs to the third NAND gate and it process the final output [(AB)’ (A’B’)’]’ which is equivalent to AB + A’B’.

To implement a three input XNOR gate using NAND gate repeat the same process. The output of a three input XNOR gate is Y = ABC’+AB’C+A’BC+A’B’C’. Now double compliment has to be taken of the output equation.
Y = ABC’+AB’C+A’BC+A’B’C’
Taking double compliment of output equation
(Y’)’ = [(ABC’+AB’C+A’BC+A’B’C’)’]’
Y = [(ABC’+AB’C+A’BC+A’B’C’)’]’
Applying De Morgan’s theorem
Y = [(ABC’)’(AB’C)’(A’BC)’(A’B’C’)’]’

Now implementation of XNOR gate using NAND gates can be started. It needs four three input NAND gates, one four input NAND gates and three single input NAND gates. Three single input NAND gates are used as NOT gates to find A’, B’ and C’. The first three input NAND gate has inputs A, B and C’ and produces output ABC’. The second three input NAND gate has inputs A, B’ and C and produces output AB’C. Third and fourth three input NAND gates have inputs A’, B and C and A’, B’ and C’ respectively and produce output A’BC and A’B’C’. These four outputs ABC’, AB’C, A’BC and A’B’C’ are used as input for four input NAND gate. The four input NAND gate finally produces output [(ABC’)’(AB’C)’(A’BC)’(A’B’C’)’]’ which is equal to ABC’+AB’C+A’BC+A’B’C’.

### IMPLEMENTATION OF XNOR GATE USING UNIVERSAL NOR GATES

A XNOR gate can be implementation using universal NOR gates. As NAND gates can be used to implement any Boolean circuit similarly NOR gate can also be used to implement any Boolean circuit. To implement circuits of XNOR gates using NOR gate their output should be in Product of Sum form.
Now the output of two input XNOR gate is Y = AB + A’B’.
Y = A’B’ + AB
Y = (A’B’ + A)(A’B’ + B)
Y = (A’ + A)(A + B’)(A’ + B)(B’ + B)
Y = (A + B’)(A’ + B)
Since (A’ + A) and (B’ + B) are equal to 1.
Now the output equation is in POS form. As double compliment has been taken in case of implementation XNOR gates using NAND gates here double compliment has to be taken.
Y = (A + B’)(A’ + B)
(Y’)’ = [{(A + B’)(A’ + B)}’]’
Now applying De Morgan’s theorem to inner compliment
Y = [(A’ + B)’ + (A + B’)’]’

Now the implementation of two input XNOR gate can be started using NOR gates. To implement this circuit it needs three two input NOR gates and two single input NOR gate to find A’ and B’ of inputs A and B. First NOR gate having input A’ and B will produce output (A’ + B)’ and the Second NOR gate having inputs A and B’ will produce output (A + B’)’. These two outputs are fed as input to third NOR gate and this NOR gate produces output [(A’ + B)’ + (A + B’)’]’. The output of three input XNOR gate is Y = ABC’+AB’C+A’BC+A’B’C’ and it is not in POS form. Therefore it needs to be changed into POS form.

Y = ABC’+AB’C+A’BC+A’B’C’
Y = ∑(0, 3, 5, 6)
Y = π(1, 2, 4, 7)
Y = (A + B + C’)(A + B’ + C)(A’ + B + C)(A’ + B’ + C’)
Now the output is in POS form. Now taking double complement of output equation Y = (A + B + C’)(A + B’ + C)(A’ + B + C)(A’ + B’ + C’).
(Y’)’ = [{(A + B + C’)(A + B’ + C)(A’ + B + C)(A’ + B’ + C’)}’]’
Y = [(A + B + C’)’ + (A + B’ + C)’ + (A’ + B + C)’ + (A’ + B’ + C’)’]’
Now the implementation of three input XNOR gate using NOR gates can be started. To implement this circuit it will need four three input NOR gates, one four input NOR gate and one single input NOR gate. Single input NOR gates are used to find A’, B’ and C’. The first three input NOR gate has input A, B and C’ and produces output (A + B + C’)’. similarly second, third and fourth three input NOR gates have inputs A, B’, C and A’, B, C and A’, B’, C’ respectively and their respective outputs are (A + B’ + c)’, (A’ + B + C)’ and (A’ + B’ + C’). These four outputs work as four inputs for four input NOR gate. And this Four input NOR gate produces the final output [(A + B + C’)’ + (A + B’ + C)’ + (A’ + B + C)’ + (A’ + B’ + C’)’]’

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