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MULTIPLEXER AND ITS TYPES

DEFINITION OF MULTIPLEXER

A Multiplexer is a combinational circuit which receives binary inputs from one of the 2n input lines and it directs these inputs to a single output. The selection of a particular input data line to the output is decided by a set of selection inputs. A 2n – to – 1. Multiplexer has 2n input lines, one output line and n selection input lines. Bit combination of Selection inputs decide that which input is directed to output. The Multiplexer or MUX is also called a data selector, because it selects one of the many input data lines and steers the binary information to the output. A 2n – to – 1 Multiplexer is shown below. Its Block Diagram, Truth Table and circuit diagram is given below.

BLOCK DIAGRAM, TRUTH TABLE AND CIRCUIT DIAGRAM

GENERAL BLOCK DIAGRAM OF MULTIPLEXER
The Block Diagram of a 2n – to – 1 MUX is shown here. It has 2n data inputs form I0 to In and n Selection inputs from Sn to S0. Y is the output of the Multiplexer. A particular input line from Ito Iis selected by the bit combinations of selection input. As for example if we want to select the input line I0 to direct it as output, we have to assign all selection inputs to 0. Similarly if we want to select input line I1 for output, all selection input lines should be 0 except selection input S0. The function table or Truth Table of a 2n – to – 1 Multiplexer is shown here. The table demonstrated below shows the relationship between the input data lines and section inputs and how the output is dependent on these two variables.The circuit diagram of a 2n – to – 1 Multiplexer is given here. The Circuit Diagram is implemented by the use of AND GateOR Gate and Invert or NOT Gates. The number of AND Gates used in the circuit is depend on the number of inputs to the Multiplexer. One OR Gate is used here which gives the final output Y. The outputs of all AND Gates are directed as inputs for the OR Gate. The circuit diagram shown here shows how the circuit works. All AND Gates except one is 0 for each combination of inputs and selection inputs. The input line which is attached with the AND Gate whose output is 1 is directed to the output.
GENERAL CIRCUIT DIAGRAM OF MULTIPLEXER USING LOGIC GATES

TYPES OF MULTIPLEXER OR MUX

On the basis of input lines and selection inputs to the Multiplexer, a Multiplexer can be classified into a number of sets for example 2 – to – 1 Multiplexer, 4 – to – 1 Multiplexer, 8 – to – 1 Multiplexer and so on.

2-TO-1 MULTIPLEXER OR 2X1 MULTIPLEXER

A 2 – to – 1 or 2X1 Multiplexer has two data inputs and one output. It has also one selection input.

BLOCK DIAGRAM, TRUTH TABLE AND CIRCUIT DIAGRAM

BLOCK DIAGRAM OF 2X1 OR 2-TO-1 MULTIPLEXER OR MUXFrom the Block Diagram of 2X1 Multiplexer shown below, it can be seen that it has two data inputs I0 and I1. The section input is S0 and Y is the output of the Multiplexer. The Truth Table of 2X1 Multiplexer is shown below. From the Truth Table we see that the selection input S0 can have only two values either it can be 1 or 0. When selection input is 0 the data input I0 is directed to the output and when selection input is 1 the data input I1 is directed to output Y.

INPUT OUTPUT
S0 Y
0 I0
1 I1

CIRCUIT DIAGRAM OF 2X1 OR 2-TO-1 MULTIPLEXER OR MUX

Where S’ denotes the complement of S. The circuit diagram of the 2X1 Multiplexer is given here. It is implemented by Logic Gates. There are two AND Gates where the first AND Gate gives output I0S’0 and the second AND Gate gives I0Sas output. One OR Gate is used here which gives the final output of the 2X1 Multiplexer. The output equation of the 2 – to – 1 Multiplexer is as follows.
Y = S’0I0 + S0I1

IMPLEMENTATION OF 4X1 MULTIPLEXER USING 2X1 MUX

4X1 MULTIPLEXER USING TWO 2X1 MULTIPLEXERSImplementation of 4X1 Multiplexer using 2X1 Multiplexer is shown below. There are two 2X1 Multiplexers MUX1 and MUX2. D0 and D1 are the inputs to MUX1 and D2 and D3 are the inputs to MUX2. The output of the MUX1 is Y1 and Y2 is the output of MUX2. The two output Y1 and Y2 are the inputs to an OR Gate whose output is Y. It is the output of the whole circuit which gives the output of a 4X1 Multiplexer. A is the enable input that makes the Multiplexers active and inactive only one at a time. When A is equal to 1 MUX1 gets active and MUX2 remains inactive and when A is 0 MUX1 remains inactive and MUX2 get active. B is the selection input to both Multiplexers it selects a particular input for its value and directs it to the output of active Multiplexer as for example when A is 1 and B is also 1 then the input D1 of MUX1 is selected and it is directed to the output Y1 of MUX1, similarly when A is 0 and B is also 0 the input D3 of MUX2 is selected and directed to the output Y2 of MUX2. The Truth Table for this implementation is shown below.
Y1 = D0A’B’ + D1A’B and,Y2 = D2AB’ + D3AB. Now, Y = Y1 + Y2
Y = D0A’B’ + D1A’B + D2AB’ + D3AB

INPUTS

OUTPUTS

     A    B

MUX1  (Y1)

MUX2   (Y2)

      Y
     0    0        D0       _      D0
     0    1        D1       _      D1
     1    0        _       D2      D2
     1    1        _       D3      D3

The above given output of Y is the output of a 4X1 Multiplexer and where B = S0. A and B are the selection inputs and D0, D1, D3 and D4 are the inputs to the Multiplexer.

4X1 MULTIPLEXER OR 4-TO-1 MULTIPLEXER

BLOCK DIAGRAM OR LOGIC DIAGRAM OF 4X1 MULTIPLEXER OR MUXA 4 – to – 1 or 4X1 Multiplexer has four inputs from I0 to I4, two selection inputs S1 and S0 and one output line Y. As we can see there are two selection inputs therefore, they can have only four possible combinations which are 00, 01, 10 and 11. When selection inputs are 00 the input line I0 is selected and it is directed to output. Similarly other inputs are directed one by one to the output Y for their combination of selection inputs. The Block Diagram of a 4 – to – 1 Multiplexer is shown below. The output equation of the 4X1 Multiplexer is given below.

Y = I0S’1S’0 + I1S’1S0 + I2S1S’0 + I3S1S0

The Truth Table of 4X1 multiple is shown below. From the Truth Table of 4X1 Multiplexer we can understand the whole operation. When S1 and S0 are equal to 1 and 0 the input I1 is joined to output. Similarly for other values of S1and S0 the remaining inputs are directed to output.

INPUT

OUTPUT
S1 S0

Y

0

0 I0
0 1

I1

1

0 I2
1 1

I3

CIRCUIT DIAGRAM OF 4X1 OR 4-TO-1 MULTIPLEXER OR MUXThe circuit diagram of the 4 – to – 1 Multiplexer is shown here. The implementation of this circuit is done by the help of AND Gate, OR Gate and NOT Gate. NOT Gates are used to get the complement values of selection inputs as shown in the picture. There are four AND Gate which give four different outputs for different values of selection inputs. The output of each AND Gate is directed as  input to OR Gate where OR Gate gives the final output of the Multiplexer.

DESIGNING LOGIC CIRCUIT DIAGRAM OF A BOOLEAN FUNCTION USING MULTIPLEXER

K MAP OF THE BOOLEAN FUNCTION Let a Boolean function given by F (A,B,C,D) = ∑(0, 5, 6, 8, 20, 14) Can be implemented by using the following stepS. First we have to find the required equation of the function in the respect of the inputs A, B,C, and D. We can find the value of F by using K-MAP. Now the required equation of F is as follow:F = BCD’ + AB’D’ + B’C’D’ + A’BC’D. We can implement the logic circuit diagram of a function using 16X1 or 16-to-1 MUX, 8X1 or 8-to-1 MUX, 4X1 or 4-to-1 MUX and 2X1 or 2-to-1 MUX. Since this function has four variables therefore, it will be implemented by 16X1 Multiplexer only. Now, the general output equation of the 16X1 MUX is as follow.

Y = IS’3S’2S’1S’+ I1 S’3S’2S’1S0 + IS’3S’2S1S’0 + I3S’3S’2S1S+ I4 S’3S2S’1S’+ I5 S’3S2S’1S+I6S’3S2S1S’0 + I7 S’3S2S1S0+ I8 S3S’2S’1S’0 + I9S3S’2S’1S0 + I10 S3S’2S1S’0+ I11 S3S’2S1S0 + I12S3S2S’1S’0 + I13 S3S2S’1S0+ I14S3S2S1S’0 + I15S3S2S1S0 Equation One (1)
Since, F (A,B,C,D) = ∑(0,5,6,8,10,14)BLOCK DIAGRAM OF BOOLEAN FUNCTION USING 16X1 MULTIPLEXER
F = m0 + m5 + m6 + m8 + m10 + m14
F = A’B’C’D’ + A’BC’D + A’BCD’ + AB’C’D’ + AB’CD’ + ABCD’
F = 1.A’B’C’D’ + 0.A’B’C’D + 0.A’B’CD’ + 0.A’B’CD + 0.A’BC’D’ + 1.A’BC’D + 1.A’BCD’ + 0.A’BCD + 1.AB’C’D’ + 0.AB’C’D + 1.AB’CD’ + 0.AB’CD + 0.ABC’D’ + 0.ABC’D + 1.ABCD’ + 0.ABCD Equation Two (2)
Now comparing Equations (1) and (2), we get
I0 = 1, I1= 0, I2 = 0, I3 = 0, I4 = 0, I5 = 1, I6 = 1, I7 = 0, I8 = 1, I9 = 0, I10 = 1, I11 = 0, I12 = 0, I13 = 0, I14 = 1, I15= 0 and S3 = A, S2 = B, S1 = C, S0= D.
Therefore, the required circuit diagram is shown here.

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